1. Field of the Invention
The present invention relates to an EEPROM as a nonvolatile memory. The present invention also relates to a write control method for the EEPROM and an IC card with the EEPROM mounted therein.
2. Description of the Related Art
FIG. 18 is a functional block diagram of a conventional IC card. Referring to FIG. 18, an IC card 1 includes a CPU 2 for processing data, to which a masked ROM 3, a RAM 4, an EEPROM 5 and an input/output circuit 6 are connected through a system bus 24. The masked ROM 3 stores processing programs for executing various functions of the IC card 1, the RAM 4 stores data temporarily required, and the EEPROM 5 stores various information required to be always stored, results of processing data, etc. The input/output circuit 6 controls transfer of data between the IC card 1 and the exterior. Specifically, the input/output circuit 6 performs parallel/serial conversion of parallel data present on the system bus 24 in accordance with an instruction from the CPU 2 and outputs the resultant serial data through an I/O terminal P5. The input/output circuit 6 also performs serial/parallel conversion of serial data input through the I/O terminal P5. Further, denoted by P1 is a V.sub.DD terminal, P2 is a GND terminal, P3 is a reset input terminal (RST terminal) for initializing the IC card 1, and P4 is a clock terminal (CLK terminal) through which an external clock signal X.sub.IN is input.
The operation of the EEPROM will be described below with reference to a structural block diagram of the EEPROM shown in FIG. 19. A memory cell array 8 has a number of word lines 8a extending from a row decoder 9 to a V.sub.PP switch 16, a number of bit lines 8b extending from a Y-gate 10 to a V.sub.PP switch 17, and memory cells 8c connected to the word lines 8a and the bit lines 8b at respective intersections of the two lines. A controller 20 is a sequence circuit having foul states, i.e., READY, LATCH, ERASE and WRITE, with an internal clock signal CLK applied as the clock. READY represents a state where the controller 20 is not brought into a write state. LATCH, ERASE and WRITE represent states where the controller 20 outputs respectively a latch signal, an erase signal and a write signal. The controller 20 enters the LATCH state upon detecting latching of data to be written into the EEPROM 5 from the exterior, stores the data on the system bus 24 in a column latch 18 sequentially, and then enters the ERASE state upon detecting a write command signal, followed by entering the WRITE state to complete writing of the data.
A timer 21 measures, based on the internal clock signal CLK, the time elapsed from latching of one data word to latching of next data word, and the time elapsed from latching of the data to input of the write command signal. If the measured time exceeds a predetermined time-out period, indicating an abnormal condition of the controller 20, the operation executed so far is invalidated, i.e., the data in the column latch 18 is canceled. When generating the erase signal and the write signal, the controller 20 also outputs a V.sub.PP generating signal to a V.sub.PP generator 19. Upon receiving the V.sub.PP generating signal from the controller 20, the V.sub.PP generator 19 boosts a source voltage V.sub.DD to produce a high voltage V.sub.PP, e.g., a voltage of 20 V, using an oscillation signal from an oscillator 22 and then supplies the high voltage V.sub.PP to both the V.sub.PP switches 16 and 17.
Further, in accordance with an address held by an address latch 23, the row decoder 9 selects one word line 8a and the column decoder 11 selects one byte of the Y-gate 10. The data on the system bus 24 is input through a data latch 15 and a write buffer 14 to the selected byte of the Y-gate 10 and is then stored in the column latch 18. On the other hand, the data read out of the memory cell array 8 is amplified by a sense amplifier 12 through the Y-gate 10 and is output to the system bus 24 through an output buffer 13.
The V.sub.PP switch 16 supplies the high voltage V.sub.PP supplied from the V.sub.PP generator 19 to the word line 8a selected by the row decoder 9, and the V.sub.PP switch 17 supplies the high voltage V.sub.PP to the bit lines 8b in accordance with the information stored in the column latch 18.
Because EEPROMs generally take a long write time, a large-capacity EEPROM has a page write function with which plural bytes of data to be written in the same page are stored in the column latch 18 and the thus-stored plural bytes of data are once written into the memory cells 8c associated with the selected word line 8a. Such a page write function enables the write time to be substantially reduced.
The conventional EEPROM is constructed and operated as described above. Therefore, when writing the same data in the same page, e.g., when shipping an EEPROM after writing fixed data, e.g., "FF", in its certain area, it is required to repeat the operation of storing the same data "FF" in the column latch 18 as many times as the number of bytes making up one page, i.e., the number of bytes connected to one word line, and to execute writing of the data into the memory cells 8c after the data of one page has been completely stored in the column latch 18. This means that the data write time has been prolonged.
Also, when writing different data, e.g., "00" and "FF" alternately, in every bytes over all the pages as needed when checking interference between the memory cells 8c in units of one byte, it is required to store the data of one page in the column latch 18, write the data of one page, and thereafter repeat the above operation to cover all the pages. This has also resulted in a prolonged data write time. Further, in the case of desiring to write the same data in all the memory cells 8c as needed when writing the data ten thousand times, for example, to check the write operation in the memory cells 8c or to check reliability i.e. the number of times of successful writing into the memory cells 8c, it is required to repeatedly latch the same data as many times as the number of bytes in one page, write the data of one page, and thereafter repeat the above operation to cover all the pages. This has similarly resulted in a prolonged data write time.
Meanwhile, because the high voltage V.sub.PP is applied to the word line 8a in the EEPROM upon data being written, a problem has been raised in that gate oxide films may be broken, for example, due to stresses caused by the high voltage V.sub.PP and the word line 8a may fail to disable writing of the data into the memory cells 8c. Additionally, since a guaranteed number of times of writing is generally determined for EEPROMs, the allowable number of times that the high voltage is applied to the word line 8a can be foreseen, but generally the guaranteed number of times of reading is not determined. This may cause trouble from stresses caused by the source voltage V.sub.DD when the voltage V.sub.DD is applied to the word line 8a for a long period of time as a result of repeating reading a number of times. Thus, there have been problems giving rise to trouble due to stresses caused by the high voltage V.sub.PP and trouble due to stresses caused by the source voltage V.sub.DD. Such troubles may also occur on the bit lines 8b besides the word lines 8a. Whether the troubles are more apt to occur on the word lines 8a or the bit lines 8b depends on the manufacturing process and the cell design, i.e., varies depending on individual products. In some cases, the word lines 8a and the bit lines 8b may both be subject to the troubles. Accordingly, reliability of EEPROMs for commercial use must be increased by checking for the presence of possible troubles and selecting good products during the test stage.